Intelligent probe card architecture

ABSTRACT

A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

BACKGROUND

1. Technical Field

The present invention relates to a probe card configuration for a testsystem used to test integrated circuits (ICs) on a wafer. Moreparticularly, the present invention relates to a probe cardconfiguration with intelligent on board features that can, for example,enable the probe card to distribute a single channel from a test systemcontroller to multiple test probes to connect to the ICs on a wafer.

2. Related Art

When testing ICs on a wafer, it is cost effective to test as manydevices as possible in parallel, thus reducing the test time per wafer.Test system controllers have evolved to increase the number of channelsand hence the number of devices that can be tested in parallel. However,a test system controller with increased test channels is a significantcost factor for a test system, as is a probe card with complex routinglines used to accommodate multiple parallel test channels. It is, thus,desirable to provide an overall probe card architecture that allowsincreased test parallelism without requiring increased test systemcontroller channels and without increased probe card routing complexity.

With limited test system controller resources, fanning out a signal froma test system controller in the probe card to multiple transmissionlines may be desirable, since the increased cost of probe card routingcomplexity will typically be outweighed by the cost of a new test systemcontroller. A test system controller has resources to enable testing afixed number of Devices Under Test (DUTs) on a wafer. With advancingtechnology, more DUTs are fabricated on a single wafer. To avoid thecost of a new test system controller, either multiple touchdowns of atest system to the wafer are performed, or the test signals normallyprovided to a single DUT are fanned out to multiple DUTs in the probecard. The later may be more desirable for burn in testing where duringheating of the wafer, multiple touch downs of the probe card to thewafer is sometimes impractical. Further, less touch downs to the waferdecrease the likelihood of damaging the wafer, and less touch downslimit wear on the probes in the test system, which may be expensive toreplace.

Fan out of the test signals in a probe card between a test systemcontroller and DUTs, however, not only increases the complexity of asystem, but also can cause inaccurate test results. To better assuretest integrity, increased circuitry can be provided on the probe card tominimize the effect of a fault on one of the fan out lines. With a testsystem having probe card fan out, a fault (short circuit) in a componentconnected on a fanned out line will severely attenuate the test signalfor all devices on the fanned out test system channels. U.S. Pat. No.6,603,323 entitled “Closed-Grid Bus Architecture For Wafer InterconnectStructure,” incorporated herein by reference, describes a solution byproviding isolation resistors between the channel line branch points andprobes to reduce attenuation caused by the faulty component. A furthersolution is provided in U.S. patent application Ser. No. 10/693,133,incorporated herein by reference, entitled “Isolation Buffers WithControlled Equal Time Delays” describing a system where isolationbuffers are used between channel line branch points and probes, withcircuitry included to assure the isolation buffers each provide auniform delay. Other problems, however, may occur with the addedcircuitry affecting test integrity, as recognized in development of thepresent invention.

With the cost of test system controller systems making their long termretention desirable, probe cards are desirable that can further take onexpanded test system functions to increase the lifecycle of an outdatedtest system. Probe cards, serving as an interface between a test systemcontroller and a wafer, are typically much less expensive than a testsystem controller, and typically replaced after a much shorter lifecyclethan the test system controller due to wear of probes on the probe card.

FIG. 1 shows a block diagram of a test system using a probe card fortesting DUTs on a semiconductor wafer. The test system includes a testsystem controller 4, or general purpose computer, connected by acommunication cable 6 to a test head 8. The test system further includesa prober 10 made up of a stage 12 for mounting a wafer 14 being tested,the stage 12 being movable to contact the wafer 14 with probes 16 on aprobe card 18. The prober 10 includes the probe card 18 supportingprobes 16 which contact DUTs formed on the wafer 14.

In the test system, test data is generated by the test system controller4 and transmitted through the communication cable 6, test head 8, probecard 18, probes 16 and ultimately to DUTs on the wafer 14. Test resultsare then provided from DUTs on the wafer back through the probe card 18to the test head 8 for transmission back to the test system controller4. Once testing is complete, the wafer is diced up to separate the DUTs.

Test data provided from the test system controller 4 is divided into theindividual test channels provided through the cable 6 and separated inthe test head 8 so that each channel is carried to a separate one of theprobes 16. The channels from the test head 8 are linked by flexiblecable connectors 24 to the probe card 18. The probe card 18 then linkseach channel to a separate one of the probes 16.

FIG. 2 shows a cross sectional view of components of a typical probecard 18. The probe card 18 is configured to provide both electricalpathways and mechanical support for the spring probes 16 that willdirectly contact the wafer. The probe card electrical pathways areprovided through a printed circuit board (PCB) 30, an interposer 32, anda space transformer 34. Test data from the test head 8 is providedthrough flexible cable connectors 24 typically connected around theperiphery of the PCB 30. Channel transmission lines 40 distributesignals from the connectors 24 horizontally in the PCB 30 to contactpads on the PCB 30 to match the routing pitch of pads on the spacetransformer 34. The interposer 32 includes a substrate 42 with springprobe electrical contacts 44 disposed on both sides. The interposer 32electrically connects individual pads on the PCB 30 to pads forming aland grid array (LGA) on the space transformer 34. Traces 46 in asubstrate 45 of the space transformer 34 distribute or “space transform”connections from the LGA to spring probes 16 configured in an array. Thespace transformer substrate 45 is typically constructed from eithermulti-layered ceramic or organic based laminates. The space transformersubstrate 45 with embedded circuitry, probes and LGA is referred to as aprobe head.

Mechanical support for the electrical components is provided by a backplate 50, bracket (Probe Head Bracket) 52, frame (Probe Head StiffenerFrame) 54, leaf springs 56, and leveling pins 62. The back plate 50 isprovided on one side of the PCB 30, while the bracket 52 is provided onthe other side and attached by screws 59. The leaf springs 56 areattached by screws 58 to the bracket 52. The leaf springs 56 extend tomovably hold the frame 54 within the interior walls of the bracket 52.The frame 54 then includes horizontal extensions 60 for supporting thespace transformer 34 within its interior walls. The frame 54 surroundsthe probe head and maintains a close tolerance to the bracket 52 suchthat lateral motion is limited.

Leveling pins 62 complete the mechanical support for the electricalelements and provide for leveling of the space transformer 34. Theleveling pins 62 are adjusted so that brass spheres 66 provide a pointcontact with the space transformer 34. The spheres 66 contact outsidethe periphery of the LGA of the space transformer 34 to maintainisolation from electrical components. Leveling of the substrate isaccomplished by precise adjustment of these spheres through the use ofadvancing screws, or leveling pins 62. The leveling pins 62 are screwedthrough supports 65 in the back plate 50 and PCB 30. Motion of theleveling pin screws 62 is opposed by leaf springs 56 so that spheres 66are kept in contact with the space transformer 34.

FIG. 3 shows an exploded assembly view of components of the probe cardof FIG. 2. FIG. 3 shows attachment of the back plate 50, PCB 30, andbracket 52 using two screws 59. Four leveling screws 62, are providedthrough the back plate 50 and PCB 30 to contact four spheres 66 near thecorners of the space transformer substrate 34. The frame 54 is provideddirectly over the space transformer substrate 34, the frame 54 fittinginside the bracket 52. The leaf springs 56 are attached by screws 58 tothe bracket 52. Two screws 58 are shown for reference, althoughadditional screws 58 (not shown) are provided around the entireperiphery to attach the leaf springs.

FIG. 4 shows a perspective view of the opposing side of PCB 30illustrating the arrangement of connectors 24 around its periphery. InFIG. 3, the connectors 24 of the PCB 30 are facing down and not shown.In typical probe cards, the connectors 24 (typically zero insertionforce (ZIF) connectors) provide flexible cable connections locatedaround the periphery of the probe card, and are configured to mate withconnectors that are typically arranged in a similar fashion on the testhead. Although illustrated as ZIF connectors, other connector types maybe used, such as pogo pins, non-ZIF flexible cable connectors,conductive elastomer bumps, stamped and formed spring elements, etc.

SUMMARY

In accordance with the present invention, a probe card is provided witha number of on board features enabling fan out of a test channel signalto multiple DUTs while limiting undesirable effects of fan out on testresults. The on board probe card features further enable enhancing testsystem controller functions, effectively increasing the lifecycle ofsome test system controllers, providing more advanced functions withoutthe cost of purchasing a more modern test system controller. The probecard in accordance with the present invention enables significant fanout with test integrity so that probe cards can be used with a limitedchannel test system controller to test a wafer with one touch down, aparticularly desirable feature during burn in tests.

On board features of the probe card include one or more of thefollowing: (a) DUT signal isolation provided by placing resistors inseries with each DUT input to isolate failed DUTs, as describedgenerally in U.S. Pat. No. 6,603,323 reference previously; (b) DUT powerisolation provided by switches, current limiters, or regulators inseries with each DUT power pin to isolate the power supply from failedDUTs, allowing a single test system controller power supply to powermultiple DUTs; (c) self test provided using an on board micro-controlleror FPGA and associated multiplexers and D/A converters, on board selftesting being necessary with fanned out test system controller resourcessince test system controller integrity checks may no longer be valid;(d) stacked or vertically oriented daughter cards provided between testsystem controller connections which form an outline area on the PCB ofthe probe card, the stacked daughter cards to accommodate additionalcircuitry used in accordance with the present invention, and to providethe additional circuitry in close proximity to the PCB, spacetransformer and other components originally forming the probe card; and(e) use of a communications bus between a controller provided on thebase PCB and separate daughter cards and the test system controller tominimize the number of interface wires between the base PCB and thedaughter cards or between the base PCB and the test system controller.The bus can further be configured to distribute analog signals to theDUTs through the use of serial to parallel D/A or A/D converters on theprobe card, providing for minimum wiring and minimum use of PCB area.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details of the present invention are explained with the help ofthe attached drawings in which:

FIG. 1 shows a block diagram of components of a conventional wafer testsystem;

FIG. 2 is a cross sectional view of a conventional probe card for thewafer test system of FIG. 1;

FIG. 3 is an exploded assembly view of components of the probe card ofFIG. 2;

FIG. 4 is a perspective view of the PCB of FIG. 2 showing connectors forconnecting to a test head;

FIG. 5 shows a cross sectional view of a probe card with on boardcomponents in accordance with the present invention; and

FIG. 6 shows a circuit diagram for components of the probe card of FIG.5; and

FIG. 7 shows an alternative circuit diagram for components of the probecard of FIG. 5.

DETAILED DESCRIPTION

FIG. 5 shows a cross sectional view of a probe card, modified from theprobe card configuration shown in FIG. 2 to include on board components,in accordance with the present invention, including daughter cards 100and 102. For convenience, components carried over from FIG. 2 to FIG. 5are similarly labeled. The daughter cards are shown in FIG. 5 asconnected by stacked connectors 104 ₁₋₄. The stacked connectors areattached to opposing card surfaces, and include male and female matingconnectors. For example connector 104 ₁ is connected to the base PCB 30,while connector 104 ₂ is connected to daughter card 100. The stackedconnectors can be ZIF, pogo pin, or other type connectors suitable forinterconnecting printed circuit boards. The connectors make the daughtercards removable so that different daughter cards can be easilyinstalled, depending on the test environment. Although shown withremovable connectors, in one embodiment, the daughter cards can berigidly connected, such as by soldering. Further, although two daughtercards are shown, a single card or more than two cards can be used,depending on design requirements.

As illustrated, the daughter cards 100 and 102 are provided in availablespacing between test system controller interface connectors 24. The testsystem controller could be a conventional Automatic Test Equipment (ATE)tester or a computer system used to control and configure the probecard, which can limit the height above the connectors 24 which thedaughter cards can be stacked. In the configuration shown, an opening isprovided in the back plate 50, forming an outline area where thedaughter cards 100 and 102 are connected to the base PCB 30. The area ofthe probe card available for daughter cards is generally dictated by thetest system controller connection and prober constraints. With limitedhorizontal spacing between test system controller interface connectors24, board area to accommodate additional circuitry for the architecturein accordance with the present invention is obtained by stackingadditional daughter cards within the outline area of the probe card.

The stacked connectors 104 ₁₋₄ provide spacing for discrete components114 provided on the surface of each of the base PCB 30 and daughtercards 100 and 102. The discrete components 114 can include bypasscapacitors for power supply lines. In one embodiment, similar discretecomponents 112 are also provided on a surface of the space transformer34. In one embodiment, the discrete components 112 are decouplingcapacitors. To accommodate the discrete components 112, a number ofspring contacts 44 are removed from the interposer 32, and rerouting oflines is provided in the space transformer 34. With the discretecomponents 112 being decoupling capacitors they are placed in closeproximity to lines carrying power to probes 16 to maximize capacitanceon the power lines that affect test results. By being placed in closeproximity to where capacitance will improve the decoupling, smallercapacitances can be used for the capacitors 110.

The daughter cards, such as 100 and 102 shown, may be redundant with thebase PCB 30, in that they carry the same discrete components on theirsurface. More redundant daughter cards can be simply added if more fanout of test channels is desired. Alternatively, the daughter cards caninclude differing components depending on test requirements andavailable space.

The daughter card 102 is shown to include a micro-controller 110 as adiscrete component 114. Although shown on daughter card 102, similarmicro-controllers can be provided on one or more of the daughter card102, daughter card 100, base PCB 30, and space transformer 34. Themicro-controller 110 may be any of a variety of programmable controllersincluding a microprocessor, digital signal processor, sequencer, FieldProgrammable Gate Array (FPGA), Programmable Logic Device (PLD) or othercontroller or device that can be programmed/configured as a controllerfor generating and providing test or control signals to electricalcircuits. In one embodiment, the micro-controller 110 is the MicrochipPIC18FXX20 with A/D capability.

The discrete components 114 on a daughter card or base PCB 30, or 112 onthe space transformer can include memory for use by the micro-controller110, or by another processor either on the probe card, or external tothe probe card. The memory can be a random access memory (RAM) providingtemporary storage, or a device providing more permanent storage such asa flash memory. To enable the micro-controller 110, or other processorto perform testing, the memory can be programmed to include test vectorsor a test program. Similarly, the memory can include systemconfiguration data.

The circuitry can also be organized such that, in concert with the DUT,a full system is created for evaluating the DUT. For example, thedaughter card and probe card circuitry could include support circuitsfor a personal computer motherboard if the DUT is an Intel or othermicroprocessor. On power up, the DUT will experience an electricalenvironment like the final use environment. In this way, a test ofoperating correctness can be performed on unpackaged DUT devices.

To accommodate the micro-controller 110 and memory, or other discretecomponents which can generate a significant amount of heat, atemperature control system can be included along with the discretecomponents 114 on the probe card daughter cards 100 and 102, or on thebase PCB 30. The temperature control system can include temperaturesensors, along with heat sinks, fans, electric coolers, heaters, orother devices needed to maintain component temperatures within a desiredrange.

Discrete components 114 in addition to the micro-controller 110 andmemory can, for example, include voltage regulators, relays,multiplexers, switches, D/A converters, A/D converters, shift registers,etc. Examples for the configuration of the discrete components are shownin the circuit diagrams of FIG. 6 and FIG. 7. Further details of thesecomponents, as well as other features included on the probe card inaccordance with the present invention are described below.

A. DUT Signal Isolation

In one embodiment the space transformer 34 includes thin film resistorsplaced in series with each probe that provides a DUT input. Such thinfilm resistors 120 ₁₋₄, providing signals from a single channel of testsystem controller 4 to inputs of DUTs 124 ₁₋₄ are illustrated in FIG. 6.As described previously, the architecture in accordance with the presentinvention uses embedded resistors, such as resistors 120 ₁₋₄, in thespace transformer 34 placed in series with each DUT input to isolatefailed or shorted DUTs from good DUT inputs. The space transformer 34,illustrated in FIG. 5, is typically a multi-layer ceramic substrate, ormay be made up of a multi-layer organic substrate, with the thin filmresistors 120 ₁₋₄ provided on one or more layers in the path of routinglines to the probes. Use of such DUT isolation resistors is described inU.S. Pat. No. 6,603,323, reference previously. In one embodiment,resistors have values ranging between 50 and 5000 ohms each. Values onthe order of 1000 ohms allow a single DUT channel to drive 10 to 100DUTs at frequencies between 5 and 50 MHz. Placement of the embeddedresistors close to the DUT is key to enabling maximum performance whileat the same time not increasing the size of the probe head. Discrete orsurface mounted resistors could also be used for this DUT isolationapplication.

In a further embodiment, as an alternative to series resistors, buffersare placed in series with each DUT input to isolate failed DUTs, asdescribed in U.S. patent application Ser. No. 10/693,133. Circuitry isthen included on a the base PCB or daughter card to assure the delayprovided in each line having a buffer is uniform, as described in theapplication Ser. No. 10/693,133.

B. DUT Power Isolation and Power Control

The system might be limited in the number of DUT power supplies it hasavailable. When using a single power supply to drive multiple DUTs, itis desirable to isolate failed or shorted DUTs from affecting the othergood devices connected to the same test system controller power supply.It is further desirable to control the power provided since a reductionof power can occur with each channel branch added.

The present architecture uses voltage regulators, current limiters orswitches in series with each DUT power pin to isolate failed DUTs. Useof voltage regulators 130 ₁₋₄ from a power supply channel 132 of thetest system controller 4 is illustrated in FIG. 6. Although shownprovided from the test system controller 4, power can likewise beprovided from separate power supplies. The voltage regulators 130 ₁₋₄have power supplied from the test system controller power supply line132, and distribute the signal power line to power multiple DUTs 124₁₋₄. The voltage regulators 130 ₁₋₄ function to isolate failed DUTs fromthe good DUTs operating from the same voltage source by detectingcurrent surges caused by a DUT with a short, or similar fault, and thencutting off or minimizing current to the DUT. Although shown as avoltage regulator in FIG. 6, the voltage regulators 130 ₁₋₄ can bereplaced by switches or current limiters with similar feedback enablingisolation of a failed DUT.

In addition to power supply isolation, the present architecture providesfor increasing power from a DUT power supply channel to enable a singlepower supply to drive more DUTs. To increase power, a DC/DC converter134 is provided on daughter card 100 between the test system controller4 and the DUT voltage regulators 130 ₁₋₄ to provide additional DUTpower. The test system controller power supplies generally have aprogrammable voltage output with a fixed maximum current. Many newsilicon devices operate at lower voltages. Hence, the test systemcontroller can be programmed to a higher voltage and the DC/DC converter134 can regulate down to a lower voltage and higher current enabling thetest system controller power supply to drive more DUTs.

To assure a precise voltage is provided to the test system, anembodiment of the present invention provides for calibration andmonitoring of the voltage regulators 130 ₁₋₄, as well as other probecard components. The micro-controller 110 is shown connected to monitorthe output of voltage regulators voltage regulators 130 ₁₋₄ to determinewhen current is cut off due to a DUT failure. In addition to receiving acurrent signal, the micro-controller 110, or other processor or discretecomponents of the probe card can be configured to calibrate the voltageregulators 130 ₁₋₄ to enable accurate control of the voltage providedfrom the regulators. Control signals can then be provided from themicro-controller 110, or other component to control the voltage outputthrough the regulators 130 ₁₋₄.

C. Probe Card Self Test

As parallelism for testing is provided by fan out in the probe card andtest functionality is moved onto the probe card, it becomes desirable toinclude features on the probe card to insure probe card test functionintegrity without requiring additional test system controllerfunctionality. In a conventional probe card, the test system controllercan generally monitor each channel for integrity. When test systemcontroller resources are distributed among several DUTs and componentsare added to isolate DUTs, probe card integrity checks made by the testsystem controller may no longer be valid checks of the test system.

Accordingly, in one embodiment shown in FIG. 6 the present architectureperforms self testing of a combination of the micro-controller 110,serial-parallel register (controller) 146, multiplexers 140 and 142, D/Aconverter 144, A/D converter 147 and other circuit components used toassure integrity of the test functions added to the probe card. Themodes of operation performed with the micro-controller 110, orprocessing units on other daughter cards or the base PCB 30 provide forself test allowing the individual daughter card PCB assemblies and basePCB assembly to be tested.

The probe card can be configured, or include software in memory toprovide for self-testing. Test results are reported from the probe cardto the test system controller 4, or other user interface. Themicro-controller 110, or other processor, can also include aprogrammable mode allowing the probe card to be reconfigured to allowprobe card testing using standard probe card test metrology tools. Oneexample of a standard metrology tool which may be used is the probeWoRxsystem manufactured by Applied Precision Inc. Use of a probe card withsuch programmable modes allows self test to be performed in the waferproduction test environment.

Apart from a self test mode, the micro-controller 110, or otherprocessor of the probe card can include a mode to monitor and report the“health” or performance of the probe card in real time. As one example,the micro-controller 110 is shown receiving the output of voltageregulators 130 ₁₋₄, illustrating its “health” reporting function if aDUT has failed. Circuitry on the probe card to provide for calibrationof the regulators 130 ₁₋₄, as well as other components of the probecard, can further assure the accuracy of “health” monitoring. Themicro-controller 110, or other circuitry on the probe card can likewisebe connected to monitor the “health” of DUTs, or to assure the base PCBand daughter card components are functioning properly and report resultsto the test system controller 4, or other user interface.

In addition to self-test and real time “health” monitoring, themicro-controller 110, or other processor of the probe card can providefor event logging. Events logged can, for example, include a testhistory, wafer statistics, pass/fail statistics, DUT site/pin failures,or other data desired when testing using the probe card. Memory includedon the probe card can be used to store the event log data.

D. Serial Bus Interface

To minimize the amount of routing lines and connector resources neededwith use of the daughter cards, a serial bus 145 is provided with thepresent architecture. The micro-controller 110 in FIG. 6 provides aserial bus interface in one embodiment to control the serial bus 145without additional area overhead. The serial bus 145 of the probe cardallows for distribution of the probe card built in self test (BIST)features with a minimum number of interface wires. The serial bus is akey enabler of the probe card BIST functionality.

The serial interface bus 145 is provided between the daughter card 100(and other daughter cards if used) and base PCB 30. The serial busenables communication between the base PCB 30 and daughter cards with aminimum number of connector and wiring resources. The serial to parallelconverter, such as serial-parallel shift register 146 is provided on thebase PCB 30 for distributing the serial bus signals to individual DUTsinternal to the PCB 30 with a minimum amount of routing lines andconnector resources.

Although shown as a simple serial-parallel shift register, theserial-parallel shifting device 146 may be a programmable controllersuch as a processor, DSP, FPGA, PLD, or micro-controller providingsimilar functionality to the micro-controller 110 on daughter card 100,with a basic function of providing parallel to serial conversion. As aprocessor, the unit 146 can also be configured to perform self testfunctions, serve to provide programming or data to other processors onthe daughter cards, and serve to provide a daisy chained connection ofprocessors through the serial bus 145.

As a processor, the serial/parallel controller unit 146 can furtherutilize compressed data formats, and can function to compress anddecompress data and test vectors. For example, the serial/parallelcontroller unit 146 can be configured to receive BCD data fromcomponents not attached to the serial bus and convert the BCD data toserial data for subsequent distribution. Similar data compression anddecompression can be provided by other programmable controllers orprocessors included on one of the daughter cards 100 and 102 or base PCB30 of the probe card.

Similarly, the serial/parallel controller unit 146 configured as aprocessor can enable the probe card to support scan test features of theDUT. Programmable logic and memory chips can have a serial scan port toprovide for scan testing. The scan port is typically used inmanufacturing to provide for a built in self test (BIST) of the chip,with the scan port not later being connected to a package lead aftermanufacture. With a connection of a DUT scan port to the serial/parallelcontroller unit, or other scan test circuitry attached to the serialbus, scan test features of the DUT can be enabled by the daughter cardeither in conjunction with or separate from the test system controller4.

The serial bus interface 133 to the test system controller 4 is furthershown in FIG. 6, providing for serial communication from the test systemcontroller 4 with a minimal number of wiring and connector resources.With the serial interface 133, the test system controller 4 can routecontrol signals to the serial to parallel converter 146, or to themicro-controller 110. The serial interface 133 can be provided from theJTAG serial port of the test system controller 4 in one embodiment, witha scan register of the test system controller 4 used to provided serialcontrol signals from the test system controller 4.

Although the test system controller 4 is shown to have a serialinterface 133 connection with the micro-controller 110, other typecommunication interfaces can be provided, such as the parallel interface135 shown. The additional interfaces can be used either in combinationwith the serial interface, or alone. Other types of interfaces caninclude RF, wireless, network, IR, or various connections as the testsystem controller 4 may have available. Although shown connected only tothe micro-controller 110, interface 135 can be connected to otherdevices on the probe card either directly or over a bus.

The serial bus 145 can also be used to distribute analog signals to andfrom the DUTs. The present architecture includes a serial digital toanalog converter 144 to convert serial signals to analog form anddistribute the signals to multiple DUTs. The D/A converter 144 receivesa test signal input through the serial bus 145 from the serial-parallelshift register 146, although the signal could be provided from othercomponents connected to the serial bus 145. The D/A converter 144 cancontain multiple D/A converters per package (typically 8, 16 or 32 perpackage) that are connected to the serial interface bus 145 fordelivering analog voltages to the DUTs with a minimum wiring and PCBarea. An A/D converter 147 is further included to receive analog signalsfrom the DUTs and convert to a digital form to provide signals over theserial bus, preferably to the serial-parallel shift register. An analogmultiplexer 142 is further provided to provide feedback from the outputsof the voltage regulators 130 ₁₋₄ to the micro-controller 110 to enablethe micro-controller to assure the voltage regulators 130 ₁₋₄ arefunctioning properly for both self test, and test integrity assurance.

FIG. 7 shows an alternative circuit diagram to FIG. 6 for componentsthat may be used on the probe card of FIG. 5. The circuit of FIG. 7modifies FIG. 6 by using an FPGA 150 to replace the serial-parallelshift register 146, as well as serial DAC 144, and serial ADC 147 on thebase PCB 30.

The FPGA 150 can include an on-board micro-controller, or beprogrammed/configured to provide the function of a micro-controller 110.The micro-controller 110 of FIG. 6 is, thus, shown removed in FIG. 7with its function assumed by FPGA 150. Similarly, the FPGA 150 of FIG. 7can be programmed to perform the function of analog multiplexer 142 ofFIG. 6. The output of voltage regulators 130 ₁₋₄ are, thus, shown inFIG. 7 provided to the FPGA 150 and the analog multiplexer 142 of FIG. 6is removed in FIG. 7. Other components are carried over from FIG. 6 toFIG. 7, and are similarly labeled.

The FPGA 150 can be programmed or configured by a program such asVerilog. Programming or configuration of the FPGA 150 can be providedprior to installation of the FPGA 150 on the probe card. Programming orconfiguration of the FPGA 150 can further be performed afterinstallation using the test system controller 4 or other user interfaceconnected to the probe card. The FPGA 150 can be reconfigured based onresponses from one or more DUTs to facilitate specific tests requiredfor the DUTs.

Programming of the FPGA may be based on the design database or testbench of the DUT. In one embodiment, the output of a Computer AidedDesign (CAD) design system used to develop the DUT may be used tosynthesize the test program loaded into the FPGA or micro-controllerprogram memory located on the probe card. The CAD design data base canbe used directly or post-processed by design or CAD tools used to designthe probe card. In this way, a standard or semi-standard daughter card,base PCB, or space transformer mounted controller assembly may be usedand customized by software for testing specific DUT designs.

The FPGA 150 is preferably located on the base PCB 150 to minimize thenumber of routing lines and connectors between a daughter card 132 andthe base PCB 30, although it is conceivable the FPGA 150 could beincluded on daughter card 100. The FPGA 150 is shown providing a serialinterface to serial bus 145 to provide efficient communications with thetest system controller 4.

F. Programmable Routing

Signal, power and ground traces in a probe card are described previouslyas being routed with some type of space transformation, either using thespace transformer 34 or base PCB 30. Once these traces are manufactured,there is little flexibility in making changes. Flexibility can be builtinto probe cards by ICs such as relays, switches, or an FPGA to providecontrollable rerouting of the traces. Using a programmable orcontrollable IC to route signals provides a great degree of flexibility,allowing the same probe card to be used for many designs by simplyreprogramming the IC. In one embodiment, the ICs are controlled orprogrammed from automatic test equipment attached to the probe, allowingtest engineers to re-program the probe card in real time as they weredebugging a test program.

In one embodiment, the FPGA 150, as shown in FIG. 7, can be configuredto provide programmable line routing. The FPGA 150 can function tocontrol routing along with providing a serial-parallel shift function,or function to control trace routing without providing anyserial-parallel shifting. Other programmable ICs, such as a PLD orsimple programmable switches, can similarly be used to provide theprogrammable trace routing.

As described previously, connectors 24 distribute signals from the testsystem controller 4 to connectors 24 of the base PCB 30. Channeltransmission lines 40 then distribute signals from the connectors 24horizontally in the PCB 30 for connection to DUTs. In one embodiment,the channel transmission lines 40 of the PCB are routed through the FPGA150 on the base PCB 30 to enable routing resources of the test systemcontroller 4 to be programmably connectable to different DUTs. The FPGA150 simply serves as a programmable switch matrix. In other embodiments,resources from the test system controller 4 are provided either seriallyor directly to an FPGA 150 on a daughtercard, or on the spacetransformer 34 to enable programmable connection of test systemcontroller resources to different DUTs. Connection to the FPGA 150either through the test system controller 4, or through a separateconnection from a user interface to the FPGA 150 on the probe cardallows the FPGA 150 to be reprogrammed to reconfigure trace routing asdesired.

F. Combined Features

The features of an architecture described in sections A-E previously canbe used either individually, or combined as test requirements maydictate. A significant increase in the ability to fan out a test signalcan be realized with features described according to the presentinvention. For example, an old generation test system controller mightbe a 32 DUT test system controller that operates at 33 MHz. Using theintelligent probe card architecture described herein, the test systemcontroller can be expanded to a 256 DUT test system controller operatingat the same 33 MHz. If the test system controller has redundancyanalysis (RA) capability, multiplexing of the DUT I/O can enableredundancy analysis testing as well. In FIGS. 6 and 7, such ability isshown with DUT I/O inputs provided through a multiplexer 140 to the testsystem controller 4. The multiplexer can be controlled bymicro-controller 110, or the processing unit 146 to route desired DUTI/Os to the test system controller 4.

This shared resource or multiplexed test configuration could be veryattractive as a wafer level step-burn-in card, where as indicatedpreviously it is desirable to test all DUTs during one touch down duringthe burn in process. The test speed might be reduced by multiplexing ofDUT I/Os, but in a burn-in situation, this would generally not belimiting. The benefit would be both a wafer level burn-in test systemcontroller solution and possible recovery from burn-in failures with RAeither running in the background or provided for in a RA sort after burnin on a separate sort operation.

Although the present invention has been described above withparticularity, this was merely to teach one of ordinary skill in the arthow to make and use the invention. Many additional modifications willfall within the scope of the invention, as that scope is defined by thefollowing claims.

1-35. (canceled) 36: A test assembly for communicating test data betweena test system controller and an unpackaged semiconductor device undertest, the unpackaged semiconductor device designed for use in anoperational environment, the test assembly comprising: a probe card forproviding connection to the test system controller to communicate testinformation with the test system controller and having a plurality ofresilient probes configured to mechanically and electrically contact theunpackaged semiconductor device to communicate signals to or from theunpackaged semiconductor device; and circuitry comprising at least aportion of the operational environment. 37: The test assembly of claim36, wherein the circuitry includes circuit portions of a personalcomputer motherboard. 38: The test assembly of claim 36, wherein anunpackaged semiconductor device is a microprocessor. 37: The testassembly of claim 36, wherein the circuitry emulates the operationalenvironment power up sequence for the unpackaged semiconductor device.38: The test assembly of claim 36, wherein the probe card furthercomprises a wiring substrate and at least a portion of the circuitryresides on the wiring substrate. 39: The test assembly of claim 36,wherein the probe card further comprises a probe support substrate andat least a portion of the circuitry resides on the probe supportsubstrate. 40: The test assembly of claim 36, wherein the probe cardfurther comprises a daughter card mechanically and electrically coupledto the probe card and wherein at least a portion of the circuitryresides on the daughter card. 41: A method of testing an unpackagedsemiconductor device with a testing assembly, the unpackagedsemiconductor device designed for use in an operational environment, themethod comprising: providing a probe card for making connection to atest system controller to communicate test information and having aplurality of resilient probes configured to mechanically andelectrically contact the unpackaged semiconductor device to communicatesignals to or from the unpackaged semiconductor device; providingcircuitry including a portion of the operational environment; bringinginto contact the resilient probes and the unpackaged semiconductordevice; and testing the unpackaged semiconductor device with thecircuitry to emulate a portion of the operational environment. 42: Themethod of claim 41, wherein the providing circuitry comprises providingsupport circuits from a desired motherboard configuration. 43: Themethod of claim 41, wherein the testing includes a power up sequence.44: The method of claim 41, wherein the circuitry emulates theoperational environment power up sequence for the unpackagedsemiconductor device. 45: The method of claim 41, wherein the providingthe circuitry comprises providing at least a portion of the circuitry ona wiring substrate. 46: The method of claim 41, wherein the providingthe circuitry comprises providing at least a portion of the circuitry ona probe support substrate. 47: The method of claim 41, wherein theproviding the circuitry comprises providing at least a portion of thecircuitry on a daughter card mechanically and electrically coupled tothe probe card. 48: A method of producing a tested semiconductor device,the semiconductor device designed for use in an operational environment,the method comprising: providing a probe card for making connection to atest system controller to communicate test information and having aplurality of resilient probes configured to mechanically andelectrically contact an unpackaged semiconductor device to communicatesignals to or from the unpackaged semiconductor device; providingcircuitry including a portion of the operational environment; bringinginto contact the resilient probes and the unpackaged semiconductordevice; and testing the unpackaged semiconductor device with thecircuitry to emulate a portion of the operational environment. 49: Themethod of claim 48, wherein the providing circuitry comprises providingsupport circuits from a desired motherboard configuration. 50: Themethod of claim 48, wherein the testing includes a power up sequence.51: The method of claim 48, wherein the circuitry emulates theoperational environment power up sequence for the unpackagedsemiconductor device. 52: The method of claim 48, wherein the providingcircuitry comprises providing at least a portion of the circuitry on awiring substrate. 53: The method of claim 48, wherein the providingcircuitry comprises providing at least a portion of the circuitry on aprobe support substrate. 54: The method of claim 48, wherein theproviding circuitry comprises providing at least a portion of thecircuitry on a daughter card mechanically and electrically coupled tothe probe card.